diff_pair: fix gf180 LVS pin labels and dummy net - #103
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Pin markers were drawn on hardcoded sky130 layer numbers -- met1_pin (67,16), met1_label (67,5), met2_pin (68,16), met2_label (68,5) -- which mean nothing on gf180. They now come from the PDK. They were also sized and placed so that the marker carried only the label layer, tangent to the port's edge rather than centred on it. The extractor then finds no conductor under the text, the net comes out unnamed, and LVS reports the pin as missing from the layout. The marker is now sized to the routable metal's minimum width and aligned centre-to-centre, so it lands inside metal the router already placed. Rebased onto current main. The `no_pin_labels()` context manager this branch originally added is dropped: ReaLLMASIC#105 landed `with_pin_labels` on diff_pair, and ReaLLMASIC#112 handles the general case in the LVS runner, where it needs no cooperation from any cell and does not depend on ambient state that `@cell` cannot see.
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Rebased onto current The What remains is the part nothing else covers. The pin markers were drawn on hardcoded sky130 layer numbers: Those mean nothing on gf180, and the marker was placed tangent to the port's edge carrying only the label layer. The extractor then finds no conductor under the text, the net comes out unnamed, and LVS reports the pin as missing from the layout — which is the shape of Two files, one commit. |
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diff_pairanddiff_pair_ibiasfail LVS on gf180 inmain. Threeseparate causes, all in how the cell describes itself rather than in its
geometry — DRC is clean before and after.
Pin labels land off metal
gf180 maps
met*_pinandmet*_labelto the same non-conducting labellayer, so a marker drawn only there has no conductor under it. The markers
were also aligned
('c','b'), which places them tangent to the port edgeinstead of on it:
current_mirroralready centres its bulk label for this reason; itscomment describes the same failure. Factored the six copy-pasted marker
blocks into one helper while there.
Dummy S/D net chosen by PDK name
The cell routes its dummies to the tap ring whenever
substrate_tapison, so both extractors report them on bulk — that follows the layout, not
the process.
diff_pair_cmirrorbiasalready had to override this back to'B', with a comment noting the standalone convention was wrong there.Same reasoning retires the
## HACK ... likely incorrectPDK check on thecmirror dummies.
Sub-cell labels leak into the parent
VTAILis a top-level pin of a standalonediff_pairbut an internal netinside
diff_pair_ibias, so the inherited label extracted as an extratop-level pin.
low_voltage_cmirrorsolves this with aGLAYOUT_NO_PIN_LABELSsave/set/restore block; this adds that as a
no_pin_labels()contextmanager in
port_utilsand uses it, rather than copy-pasting the block.Validation
Ran the repo's own runners on both PDKs:
opampstill fails LVS on gf180 (unchanged by this PR). Its nwell tapstack tops out one via below the vdd rail, so the nwell extracts as an
unnamed net and every PMOS bulk goes with it — happy to open that
separately with the measurements.